1. Field of the Invention
The present invention relates generally to a processor register, and more particularly, to a segment allocation method of expanding an RISC (reduced instruction set computer) processor register.
2. Description of the Related Art
As technology develops very quickly, it has not been difficult for adding a physical register into a CPU (central processing unit) in hardware. However, before the register is added, the existing ISA (instruction set architecture) must be changed and registers cannot be effectively applied and the code size fails to be reduced, so the compilers of 32 registers are still in the majority.
To improve the executive performance, the instruction level parallelism is applied more and more to currently available processors and compliers. However, development of high instruction level parallelism and relevant optimization needs a lot of registers as support. Besides, in the embedded system, limited memory capacity and low power consumption further highlight the significance of lots of registers. Pitifully, the number of the registers fails to be greatly increased subject to some traditional
In the architecture of the RISC commonly applied to the embedded system, there are 32 registers, so one instruction includes three register fields 91 (Rd, Rt, and Rs) at most and the code space of each register field 91 is 5 bits. Taking MIPS (millions of instructions per second) as an example, the distribution state of the each register field in the instruction is shown in FIG. 4. In such encoding, each of the register fields is 5-bit, so the number of the register corresponding to each register field is 25=32. In other words, such encoding has limited the number of the registers to 32.
If the code space of adding the register field is one bit, the required capacity for one instruction may be increased up to 2-3 bits. For example, in an Alpha instruction set, the code space of the register field takes 28%; in an ARM instruction set, it takes 25%. Thus, if the code space of the register field is changed, the code will be greatly affected, as well as the hardware, e.g. decoding stage in the pipeline, stretching clock cycles, or increasing power consumption. Under the circumstances, it is infeasible to increase the number of the registers by enlarging the code space of the register field.
In light of the above, the number of the registers cannot be increased primarily because of influential factors such as the code size. Nevertheless, such limitation is adverse to the growth of the performance to decrease some possibilities of optimization. For example, when the register is insufficient, it is necessary to spill the registers out to the memory. However, when the register is sufficient, such process is not very necessary and it may be adverse to the performance because what it takes for access to the memory is slower than that of the internal process of the processor, such as accessing the register. Therefore, it is unattainable for the existing technology to increase the number of the registers.